Accelerator
One execution layer for every device you own.
Accelerator is a .NET service that runs computation plans on whatever hardware is in the machine or on the network. That includes a CPU SIMD baseline, Graphcore IPUs, Intel GPUs, CUDA and OpenCL GPUs, FPGAs, DMA engines, and RDMA links. You describe the work once as a plan. Accelerator finds the devices, scores them, compiles the plan for the ones it picks, caches the result, and executes it. Your application code doesn't change when the hardware does.
Hardware Acceleration Targets
Accelerator dynamically scores, selects, and dispatches computation across heterogeneous devices based on live capability declarations.
Graphcore IPU
First-class IPU device models, Poplar error mapping into typed .NET exceptions, special compute units with ring-pipe configuration solving, and sidecar capacity reservations.
Intel GPU
Direct SPIR-V and native Zebin dispatch via LevelZero.NET, typed USM shared-memory buffers, multi-device affinity scoring, and hardware execution telemetry.
CUDA & OpenCL GPU
Pluggable driver wrappers for NVIDIA CUDA and cross-platform OpenCL GPUs with automatic memory pinning, capability discovery, and asynchronous command queues.
FPGA & Swarm Fabric
Hardware-level agent message routing, spatial compute blocks, and direct swarm metaheuristic algorithm offloading over high-throughput low-latency fabrics.
DMA, RDMA & NVMe
Kernel-bypass RDMA interconnects, direct memory access (DMA) engines, and high-throughput NVMe streaming channels across clustered compute nodes.
Host Abstractor (CPU)
Vectorized CPU-side baseline with AVX-512 and ARM Neon acceleration, serving as a guaranteed fallback execution target when specialized devices are unavailable.
End-to-End Orchestration Capabilities
From plan submission to distributed execution, caching, telemetry, and automated memory tiering.
One Plan, Many Backends
Applications submit structured computation plans via PlanEnvelope. AcceleratorManager handles backend discovery, lifecycle, hardware capability scoring, and automatic multi-device dispatch.
Dual Operating Models
Distinguishes execution models from programming models. Intel GPUs execute SPMD while Graphcore IPUs execute BSP. Contract validators enforce behavioral semantics across mixed clusters.
Compile Once, Reuse
Content-addressed SHA-256 plan hashing identifies identical work. An in-memory and disk compiled-graph cache bypasses recompilation, supporting multi-device segment propagation.
First-Class IPU Architecture
IPUs receive dedicated device models, typed Poplar exception mappers, ring-pipe configuration solvers, and sidecar reservation services for compute-adjacent observer graphs.
Tiered KV-Cache for LLMs
Places large LLM key-value states across VRAM, host pinned memory, and NVMe buffers. An address map and directory engine enable context lengths exceeding single-device capacity.
Remote & Distributive Dispatch
Dispatches computation fragments to remote worker nodes across the local network. Real-time Level Zero and ring-pipe telemetry quantify latency and throughput bottlenecks.
Observable by Default
Full execution telemetry, runtime topology snapshots, and capability maps allow operators to inspect exactly what ran on which device and why the scheduler selected it.
PowerShell Operations Module
Hardware discovery, device ranking, and fabric orchestration ship as native PowerShell cmdlets and scripts for DevOps automation, continuous integration, and ops workflows.
Dual Operating Models: SPMD & BSP
Accelerator declares execution and programming models per backend, validating contracts so mixing device types never hides behavioral semantics.
| Architectural Dimension | Intel GPU (Level Zero) | Graphcore IPU (Poplar) |
|---|---|---|
| Primary Execution Model | SPMD (Single Program, Multiple Data) | BSP (Bulk-Synchronous Parallel) |
| Memory Architecture | Unified Shared Memory (USM / Device Pinned) | In-Processor SRAM per Tile (Super-fast local) |
| Synchronization Pattern | Work-group Barriers & Command Events | Strict Compute-Exchange-Sync Supersteps |
| Error Representation | Level Zero Result Codes & Exception Mapping | Poplar Engine Exception Translation |
| Orchestration Primitive | LevelZero.NET Command Queues | Poplar Ring-Pipe Streams & Engine Sessions |
| Observer Sidecar Support | Async Event Polling & Timestamps | Reserved Tile Capacity & Sidecar Advice |
Compile Once, Reuse
Plan compilation is isolated from execution. Content-addressed plan hashing ensures repetitive computations avoid redundant compilation cycles.
Cryptographic hash derived from graph topology, operator signatures, parameter types, and tensor dimensions.
Maintains serialized IPU Poplar executable streams and compiled Level Zero Zebin modules ready for instant execution.
Multi-backend plans are automatically partitioned into contiguous device segments with managed DMA/RDMA boundaries.
KV-Cache Tiering for LLMs
Overcomes single-device memory limits for large context window language models through hierarchical storage tiering.
High-priority attention heads and recent token states remain locked in ultra-fast device VRAM or host pinned RAM.
Tracks page offsets across VRAM, host system memory, and streaming NVMe storage for sub-millisecond retrieval.
Direct bridge enabling Hypertensor GraphRAG and ML Suite inference engines to stream KV state asynchronously.
Why This Exists
“Compute shouldn't be locked to one vendor's stack. Accelerator lets a workstation with an older IPU card, an Intel GPU and a few dozen CPU cores act as one machine. It is the hardware foundation under the rest of the suite: the ML libraries, the swarm optimizers and Hypertensor GraphRAG all reach devices through it.”
Unify Your Hardware Compute Under One Layer
Deploy computation plans across IPUs, GPUs, and CPUs without rewriting application code. Explore the open repositories or read our operator guides.