Component Library

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This section is an auto-generated index of all reusable FPGA modules and components in this project. Each entry links to a dedicated page with complete Verilog/SystemVerilog source code, architectural descriptions, interface specifications, and integration notes.

Component Index

80+ components and counting, across utility modules, BMC components, DDR3 controller components, DMA engine components, host interface components, interrupt controller components, IOMMU components, Graphcore IPU interface components, NVMe controller components, P2P communication components, PCIe endpoint and HIP unlock components, power management components, testbench components, and timing/PTPv2/synchronization components.

Utility Modules

• Width Converter (width_converter.v)
• Width Adapters (width_adapters.v)
• CDC Modules (cdc_modules.v)
• Clock Domain Crossing (clock_domain_crossing.v)
• Skid Buffer (skid_buffer.v)
• Synchronous FIFO (fifo_sync.v)
• Asynchronous FIFO (fifo_async.v)
• Round-Robin Arbiter (arbiter_rr.v)
• Error Injector (error_injector.v)
• Advanced Error Recovery (advanced_error_recovery.v)

BMC & Management Components

• BMC Mailbox (bmc_mailbox.v)
• GPIO Controller (gpio_controller.v)
• I2C Master (i2c_master.v)
• IPMI Bridge (ipmi_bridge.v)
• NC-SI Controller (ncsi_controller.v)
• Thermal Interface (thermal_interface.v)

DDR3 Controller Components

• DDR3 SDRAM UniPHY Wrapper (ddr3sdram_uniphy_iommu.v)
• DDR3 UniPHY Core Assembly (ddr3sdram_uniphy_iommu_0002.v)
• AFI Mux DDR3 DDRx (afi_mux_ddr3_ddrx.v)
• DDR3 P0 ACV LDC (ddr3sdram_uniphy_iommu_p0_acv_ldc.v)
• DDR3 P0 Addr/Cmd Datapath (ddr3sdram_uniphy_iommu_p0_addr_cmd_datapath.v)
• DDR3 P0 Addr/Cmd LDC Pad (ddr3sdram_uniphy_iommu_p0_addr_cmd_ldc_pad.v)
• DDR3 P0 Addr/Cmd LDC Pads (ddr3sdram_uniphy_iommu_p0_addr_cmd_ldc_pads.v)
• DDR3 P0 Addr/Cmd Non-LDC Pad (ddr3sdram_uniphy_iommu_p0_addr_cmd_non_ldc_pad.v)
• DDR3 P0 ALTDQDQS Bridge (ddr3sdram_uniphy_iommu_p0_altdqdqs.v)
• DDR3 P0 Clock Pair Generator (ddr3sdram_uniphy_iommu_p0_clock_pair_generator.v)
• DDR3 P0 FR Cycle Extender (ddr3sdram_uniphy_iommu_p0_fr_cycle_extender.v)
• DDR3 P0 FR Cycle Shifter (ddr3sdram_uniphy_iommu_p0_fr_cycle_shifter.v)
• DDR3 P0 ISS Probe (ddr3sdram_uniphy_iommu_p0_iss_probe.v)
• DDR3 P0 New IO Pads (ddr3sdram_uniphy_iommu_p0_new_io_pads.v)
• DDR3 P0 Read FIFO Hard (ddr3sdram_uniphy_iommu_p0_read_fifo_hard.v)
• DDR3 P0 Read Valid Selector (ddr3sdram_uniphy_iommu_p0_read_valid_selector.v)
• DDR3 P0 Reset Control (ddr3sdram_uniphy_iommu_p0_reset.v)
• DDR3 P0 Reset Sync (ddr3sdram_uniphy_iommu_p0_reset_sync.v)
• DDR3 P0 Write Datapath (ddr3sdram_uniphy_iommu_p0_write_datapath.v)

DMA Engine Components

• DMA Engine Top (dma_top.v)
• DMA Descriptor Fetch (dma_desc_fetch.v)
• DMA Scheduler (dma_scheduler.v)
• DMA Scheduler (Work-Stealing) (dma_scheduler_worksteal.v)
• DMA Read Engine (dma_read_engine.v)
• DMA Write Engine (dma_write_engine.v)
• DMA Completion Handler (dma_completion.v)
• DMA Address Generator (dma_addr_gen.v)
• DMA FIFOs (dma_fifos.v)
• Scatter-Gather Engine (scatter_gather_engine.v)
• Agent Message Router (agent_message_router.v)
• Inline Transform Engine (inline_transform_engine.v)
• PTP Clock (ptp_clock.v)
• QoS Bandwidth Controller (qos_bandwidth_controller.v)
• Telemetry Collector (telemetry_collector.v)

Host Interface Component

• Well-Behaved Host Interface (well_behaved_host.v)

Interrupt Controller Component

• MSI-X Controller (msix_ctrl.v)

IOMMU Component

• IOMMU Page Table Walker (iommu_page_table_walker.v)

Graphcore IPU Interface Components

• IPU Gateway PCIe Bridge (ipu_gateway_pcie.v)
• IPU Tile Router (ipu_tile_router.v)
• IPU Exchange Buffer (ipu_exchange_buffer.v)
• IPU Sync Controller (ipu_sync_controller.v)

NVMe Controller Components

• NVMe Controller (Complete) (nvme_controller_complete.v)
• NVMe Queue Handler (nvme_queue.v)
• NVMe MMIO Interface (nvme_mmio.v)
• NVMe Physical Layer Interface (nvme_phy.v)

P2P Communication Components

• P2P DMA Controller (p2p_dma_controller.v)
• P2P TLP Generator (p2p_tlp_generator.v)
• P2P Address Decoder (p2p_address_decoder.v)
• IPU Gateway Shim (ipu_gateway_shim.v)
• GPUDirect Interface (gpudirect_interface.v)

PCIe Endpoint Components & HIP Unlock Components

• PCIe Endpoint (pcie_endpoint.v)
• Stratix V PCIe HIP Wrapper (stratix_v_pcie_hip.v)
• Stratix V PCIe HIP Wrapper (Enhanced) (stratix_v_pcie_hip_enhanced.v)
• PCIe HIP Wrapper Example (pcie_hip_wrapper.v)

Power Management Components

• Power Management (power_management.v)

Testbench Components

• DMA Engine Testbench (tb_dma_engine.v)
• New Features Testbench (tb_new_features.v)

Timing, PTPv2, & Synchronization Components

• Catapult PTP Grandmaster (catapult_ptp_grandmaster.sv)
• PTP Hardware Clock (ptp_hardware_clock.sv)
• Ethernet Timestamp Unit (ethernet_timestamp_unit.sv)
• OCXO Discipline Loop (ocxo_discipline_loop.sv)
• LEA-M8T Interface (lea_m8t_interface.sv)
• PCIe BAR Registers (PTP) (pcie_bar_registers.sv)
• UART Receiver (uart_rx.sv)
• UART Transmitter (uart_tx.sv)
• PTP Clock (ptp_clock.v)