FPGA Book Summary & Table of Contents
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INTRODUCTION INTRODUCTION

FPGA Book Summary & Table of Contents

Table of Contents and navigation index for the FPGA PCIe DMA Engine production readiness book.

FPGA Book Summary

Part I — Production Readiness

  1. Chapter 0 — Overview
  2. Chapter 1 — Enhancements Implemented
  3. Chapter 2 — Component Library Index
  4. Chapter 3 — Production Roadmap
  5. Chapter 4 — Design Summary & Verification Checklist

Part II — Component Library Deep-Dives

Browse the categorized Component Library containing over 80 production HDL modules across:

  • Utility & Safety Primitives: Width Converter, CDC Modules, Skid Buffers, Sync/Async FIFOs, Arbiters, Error Recovery
  • DMA Engine Core: Top Integration, Descriptor Fetch, Deterministic Schedulers, Work-Stealing, Read/Write Engines, Completion Queues, Scatter-Gather
  • PCIe & Hard IP: Gen3 x8 Endpoint, Stratix V HIP Wrappers, BAR Registers
  • NVMe Storage Plane: Complete Controller, MMIO Registers, Queue Handler, Physical Layer
  • P2P & Agent Mesh: Agent Message Router, GPUDirect RDMA, IPU Gateway Shim, P2P TLP Generator
  • Timing & IEEE 1588 PTPv2: Catapult Grandmaster, PHC, OCXO Discipline Loop, Ethernet Timestamp Unit, LEA-M8T GPS Interface
  • BMC & Management: Mailbox, I2C Master, GPIO, Thermal Monitoring, IPMI Bridge, NC-SI
  • Memory & DDR3 Controller: UniPHY Wrappers, AFI Mux, Datapaths, Phase Timing & IO Pads

Part III — Appendix